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CSM Design Verification Lead

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CSM Design Verification Lead– job post

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Santa Clara Valley, CA 95014


Posted: Jun 21, 2021
Role Number:200201369
Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We are looking for a remarkable Design Verification Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of mobile power solutions. CSM DV is a group of veteran DV engineers with an extensive technical background. As a CSM DV lead, you will manage our silicon vendor’s entire DV process, starting from attributes plan to DV metrics/reports review. You will provide the technical guidance on methodology and implementation. When necessary, you will dive into the specific technical issue and help the vendor through the finish line. CSM DV lead will track and manage vendor’s DV/AMS execution, help with prioritization and mitigation when issue arises. You will also travel on a regular basis (on average once every 6 weeks) for vendor reviews (domestic and international).
Key Qualifications
  • Advanced knowledge of SOC/Display/Audio & System architecture/design and in-depth knowledge of the state of the art verification flow.
  • Experience with verification environment, including SystemVerilog / UVM / VMM.
  • Knowledge of industry standard interfaces, deep understanding of Verilog, Verilog simulator and debug.
  • Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology and philosophy.
  • Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus.
  • Should be a phenomenal teammate with excellent social skills and the passion to take on diverse challenges.
You will be responsible for ensuring the quality of the chip and you are expected to: – Work closely with internal and external teams to review specifications, improve DV plans and methodologies, and ensure full test coverage. – Collaborate with design and micro-architecture teams to understand the functional and performance goals of the design. – Lead and track DV progress. Review DV metrics. Provide technical guidance to DV implementation and execution. – Have strong communication skills, reciprocal approaches, and excellent multi-functional capabilities. – Travel for vendor reviews (destination could be domestic or international) – Take initiative in DV team building such as new technology exploring, knowledge sharing.
Education & Experience
BSEE / MSEE or MSCE with industry experience over 10 years.
Additional Requirements

Some travel is necessary.


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